Cypress CY62158EV30 Manual do Utilizador Página 67
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1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Document Number: Rev
Sheet
Date:
of
8/20/2009
22
B
Drawing Title:
Page Title:
Size
B
SRAM, Power, JTAG
FPGA board for DK-EPI
3.3V
DONE
72
PROG_B
1
TCK
110
TDI
144
TDO
109
TMS
108
U1F
XC3S100E-4TQG144C
VCCAUX
137
VCCAUX
65
VCCAUX
30
VCCAUX
102
VCCINT
80
VCCINT
9
VCCINT
45
VCCINT
115
VCCO_0
138
VCCO_0
121
VCCO_1
100
VCCO_1
79
VCCO_2
42
VCCO_2
64
VCCO_2
49
VCCO_3
13
VCCO_3
28
U1G
XC3S100E-4TQG144C
GND
133
GND
11
GND
19
GND
27
GND
37
GND
46
GND
55
GND
61
GND
90
GND
99
GND
118
GND
127
GND
73
U1H
XC3S100E-4TQG144C
2.8V
C7
4.7uF
C9
4.7uF
5V
R12
330
PWR
D1
GREEN_LED
R13 10K
C10
0.1uF
3.3V
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MA16
C5
0.1uF
C6
0.1uF
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MA17
MA18
MA19
MCS_n
MWE_n
MOE_n
GND
4
VCC
7
1OE
1
1LE
48
2D2
35
2D3
33
2D4
32
2D5
30
2D6
29
2D7
27
2D8
26
2D1
36
2Q1
13
2Q2
14
2Q3
16
2Q4
17
2Q5
19
2Q6
20
2Q7
22
2Q8
23
1D1
47
1D2
46
1D3
44
1D4
43
1D5
41
1D6
40
1D7
38
1D8
37
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1Q5
8
1Q6
9
1Q7
11
1Q8
12
2OE
24
2LE
25
GND
45
GND
10
GND
39
GND
15
GND
34
GND
21
GND
28
VCC
42
VCC
18
VCC
31
U3
74LVC16373
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
3.3V
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
MA[20..0]
MAD[7..0]
3.3V
1.2V
2.5V
A0
3
D0
9
A1
4
A2
5
A3
6
A4
7
A5
16
A6
17
A7
18
A8
19
A9
20
A10
26
A11
27
A12
28
D1
10
D2
13
D3
14
D4
31
D5
32
D6
35
D7
36
A13
29
A14
30
A15
38
A16
39
A17
40
A18
41
NC
1
NC
2
NC
21
NC
22
NC
23
NC
24
NC
43
NC
44
WE
15
OE
37
CE
8
VSS
12
VSS
34
VDD
11
VDD
33
A19
25
NC_A20
42
1Mx8
U4
IS61WV10248
MA20
ALE1
ALE2
MCS_n
MWE_n
MOE_n
BANK 3
IO
10
IO
29
IO_L10N_3
35
IO_L10P_3
34
IO_L09N_3
33
IO_L09P_3
32
IO_L08N_3
26
IO_L08P_3
25
IO_L07N_3/LHCLK7
23
IO_L07P_3/LHCLK6
22
IO_L06N_3/LHCLK5
21
IO_L06P_3/LHCLK4/TRDY2
20
IO_L05N_3/LHCLK3/IRDY2
17
IO_L05P_3/LHCLK2
16
IO_L04N_3/LHCLK1
15
IO_L04P_3/LHCLK0
14
IO_L03N_3
8
IO_L03P_3
7
IO_L02N_3/VREF_3
5
IO_L02P_3
4
IO_L01N_3
3
IO_L01P_3
2
U1D
XC3S100E-4TQG144C
X_CCLK
X_INIT_B
X_DAT
R9
330
2.5V
R8
10K
2.5V
DO
1
CLK
3
OE/RESET
8
TDO
17
VCCINT
18
1Mbit
CE
10
CF
7
CEO
13
TMS
5
VCCO
19
VCCJ
20
GND
11
NC
2
TCK
6
NC
9
TDI
4
NC
12
NC
14
NC
15
NC
16
U2
XCF01S
R11
10
R7
10K
3.3V
5V
C22
10uF
C14
0.1uF
C13
0.1uF
R18
61.9K
R16
36.5K
R17
15.4K
VIN
1
VOUT
5
SHDN
3
GND
2
NR
4
U6
TPS79228
C8
0.1uF
1
23
Q1
FDN338P
5V
1.2V
1
23
Q2
FDN338P
5V
3.3V
C16 10pF
2.5V
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MA16
MA17
MA18
MA19
MA20
MAD0
L1
6.8uH
L2
6.8uH
R10
0.033
R14
0.033
C19
1500pF
C20
1500pF
C21
1500pF
5V
C33
0.1uF
C34
0.1uF
C35
0.1uF
C36
0.1uF
C37
0.1uF
C38
0.1uF
C39
0.1uF
C40
0.1uF
C25
0.1uF
C26
0.1uF
C27
0.1uF
C29
0.1uF
C30
0.1uF
C31
0.1uF
C46
10uF
R15 61.9K
3.3V
GND
6
VIN1
13
VIN2
8
VIN3
20
EN1
17
EN2
4
EN3
3
SS1
16
SS2
5
SS3
19
IS1
12
IS2
9
SW1
14
SW2
7
FB1
11
FB2
10
FB3
2
VOUT3
1
GND
15
GND
PAD
AGND
18
U5
TPS75003
L3
3.3uH
L4
3.3uH
2.8VA
2.8VD
C43
0.1uF
C44
0.1uF
C45
0.1uF
1 2
3 4
SW1
Tactile Switch
D2
SS22
D3
SS22
C42
10uF
C41
0.1uF
C28
0.1uF
C32
0.1uF
C47
10uF
+
C11
68uF
+
C12
68uF
+
C18
68uF
L1N
L2N
C15
0.1uF
L_BL
1
5V
J5
HDR-1X1
TP1
TP2
TP3
12
34
56
78
910
12
1314
11
Xilinx JTAG
J3
2X7 HDR-SHRD
1
2
3
4
5
6
JTAG
J4
HDR-1X6
2.5V
C17
0.1uF
TDI
TMS
TDO
TCK
TP1
TP2
TP3
SRAM, Power, JTAG
- User’s Manual 1
- Copyright 2
- Table of Contents 3
- 4 September 5, 2010 4
- List of Figures 5
- List of Tables 6
- CHAPTER 1 7
- 8 September 5, 2010 8
- September 5, 2010 9 9
- Development Kit Contents 10
- Block Diagram 11
- 12 September 5, 2010 12
- Hardware Description 13
- CHAPTER 2 13
- Clocking 14
- Power Supplies 15
- Debugging 16
- Color QVGA LCD Touch Panel 17
- Control Interface 18
- Backlight 18
- Resistive Touch Panel 18
- User Switch and LED 19
- 20 September 5, 2010 20
- Peripheral Interface (EPI) 21
- CHAPTER 3 21
- 22 September 5, 2010 22
- CHAPTER 4 23
- 24 September 5, 2010 24
- Schematics 25
- APPENDIX A 25
- Schematic page 1 26
- Schematic page 2 27
- Schematic page 3 28
- Schematic page 4 29
- SDRAM Expansion Board 30
- EPI Signal Breakout Board 30
- Schematic page 6 31
- 32 September 5, 2010 32
- Component Locations 33
- APPENDIX B 33
- 34 September 5, 2010 34
- Center Positive (+) 35
- 36 September 5, 2010 36
- APPENDIX D 37
- 40 September 5, 2010 40
- Expansion Board 41
- APPENDIX E 41
- 42 September 5, 2010 42
- Remove board 42
- Remove jumpers 42
- 44 September 5, 2010 44
- Memory Map 45
- Flash, SRAM 47
- LCD Interface 48
- LCD_DECODE CPLD 48
- APPENDIX F 49
- Installation 50
- Using the Widget Interface 53
- Register Descriptions 55
- System Control Register 56
- Interrupt Enable Register 57
- Interrupt Status Register 57
- Memory Page Register 58
- Test PadRegister 58
- LCD Control Register 58
- 60 September 5, 2010 60
- Memory Port Register 61
- Memory Window Register 61
- Installing the Software 62
- Modifying the Default Image 62
- Default FPGA Image Blocks 62
- EPI Signal Descriptions 63
- EPI, LCD, Camera I/F 66
- SRAM, Power, JTAG 67
- Tactile Switch 67
- 68 September 5, 2010 68
- APPENDIX G 69
- Male EPI expansion connector 71
- Bottom side of EM2 module 71
- 72 September 5, 2010 72
- EM2 Expansion Board 78
- References 79
- APPENDIX H 79
- 80 September 5, 2010 80
- IMPORTANT NOTICE 81
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