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Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010 43
Hardware Description
The Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module
configured in Host Bus 8 address/data multiplexed mode. This mode requires the use of an
external 8-bit latch for storing the lower 8 address lines A[7:0] transmitted during the address
phase of an EPI transfer. This latch can be seen on the expansion board block diagram shown in
Figure E-3.
Figure E-3. Flash/SRAM/LCD IF Expansion Board Block Diagram
Functional Description
The Flash and SRAM memory expansion board schematics are described in this section. The first
page of the schematics shows the memory devices and address latch part of the design. The
second page shows the LCD I/F and regulator.
Flash/SRAM (Schematic 1 on page 47)
Page 1 of the schematics shows the EPI connector, address latch, and memory devices.
EPI Connector
The EPI connector J1 is a 50-pin receptacle with 0.5 mm pitch that plugs into the EPI header on
the DK-LM3S9B96 board. The 32 EPI signals and the 2 I
2
C0 signals from the LM3S9B96 are
provided on this connector. It also provides 5 V for the on-board DC regulator. Note that not all EPI
signals are used in this design.
MA[7:0]
MAD[7:0]
EPI[27:8]
EPI[7:0]
OEn
WRn
EPI30
EPI
Connector
FLASH/SRAM/LCD IF Board
DQ
L
MA[27:8]
ALE
MA27
EPI29
EPI28
MAD[7:0]
A
D
SRAM
WE
OE
1MB
A
D
FLASH
WE
CS
OE
8MB
LCD
Connector
LCD Control
LCD
DECODE
LCD Data
CE2
MA27
MA26
CE1
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