Cypress CY62158EV30 Manual do Utilizador descarregar pdf (Página 58)

58 September 5, 2010

VCFEI Video capture frame end interrupt. Clear the interrupt by setting the corresponding

bit to 1. Setting the bit to 0 has no effect.

VRMI Video capture row match interrupt. Clear the interrupt by setting the

corresponding bit to 1. Setting the bit to 0 has no effect.

LTSI LCD transfer start interrupt. Clear the interrupt by setting the corresponding bit to

1. Setting the bit to 0 has no effect.

LTEI LCD transfer end interrupt. Set to 1 to clear the corresponding bit. Clear the

interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

LRMI LCD display row match interrupt. Clear the interrupt by setting the corresponding

bit to 1. Setting the bit to 0 has no effect.

Memory Page Register

The Memory Page register selects to memory page to access.

Test PadRegister

The Test Pad register is used to access the on-board test pads TP1-TP8, which are connected to

unused FPGA pins.

Bit Name Description

TP1-TP3 Test Pins 1-3. These are connected to FPGA I/O pins. Writing a 1 sets the

corresponding test pin output to 1. Writing a 0 sets the corresponding test pint

output to 0. Reading these bits returns the value at the corresponding test pin

input.

NOTE: The FPGA output driver for these signals is always enabled.

TP4-TP8 Test Pins 4-8.These are connected to FPGA input pins. Writing these bits has no

effect. Reading these bits returns the value at the corresponding test pin input.

LCD Control Register

The LCD Control register is implemented as a set/clear register and contains four bits for LCD

panel control. To set a bit, set the corresponding bit to 1 when writing to the LCD Control Set

Table F-6. Test Pad Register

TXPAD: 0xA000.000A

15 14 13 12 11 10 9 8

00000000

R R R R R R R R

76543210

TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1

R R R R R R/W R/W R/W

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 80 81

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Cypress CY62158EV30 Manual do Utilizador Página 58