
Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010 45
Memory Map
The DK-LM3S9B96-EXP-FS8 expansion board memory map is shown in Table E-1 and Table E-2
shows the LCD Latch register.
The LCD Latch register is implemented as a set/clear register. To set a bit, the corresponding bit
must be set when writing to the LCD Latch Set register. To clear a bit, the corresponding bit must
be set when writing to the LCD Latch Clear register.
XN When clear, the L_XN signal is set to clear. When set, the L_XN signal is tri-stated. This
signal is used for the X- input to the touchscreen.
YN When clear, the L_YN signal is set to clear. When set, the L_YN signal is tri-stated. This
signal is used for the Y- input to the touchscreen.
RST When clear, the L_RSTN signal is set to clear. When set, the L_RSTN signal is reset. This
signal is used to reset the LCD panel.
Table E-1. Flash and SRAM Memory Expansion Board Memory Map
Device A[27:26] A[2:0] Description Access Base address
FLASH 0X XXX Flash memory (8 Megabytes) R/W 0x6000.0000
SRAM 10 XXX SRAM (1 Megabyte) R/W 0x6800.0000
CPLD
11 000
LCD latch set R/W 0x6C00.0000
11 001
LCD latch clear R/W 0x6C00.0001
LCD
11 010
LCD command port R
a
/W
a. For reads to the LCD Command and Data Port registers, the corresponding LCD Port Read Start register must be read first,
followed by a 500 nsec delay before reading this register.
0x6C00.0002
11 011
LCD data port R
a
/W 0x6C00.0003
LCD
11 110
LCD command port read start R 0x6C00.0006
11 111
LCD data port read start R 0x6C00.0007
Table E-2. LCD Latch Register
7 6 5 4 3 2 1 0
Reserved RST YN XN
0 0 0 0 0 R/W R/W R/W
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