Cypress Perform nvSRAM Manual do Utilizador

PRELIMINARYCY14B102L, CY14B102N2 Mbit (256K x 8/128K x 16) nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 40

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 10 of 24Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 15, 19]Figure 8. SRA

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 11 of 24Figure 9. SRAM Write Cycle #2: CE Controlled[3, 18, 19, 20]Figure 10. SRAM

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 12 of 24AutoStore/Power Up RECALLParameters Description20 ns 25 ns 45 nsUnitMin Max

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 13 of 24Software Controlled STORE/RECALL CycleIn the following table, the software c

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 14 of 24Hardware STORE CycleParameters Description20 ns 25 ns 45 nsUnitMin Max Min M

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 15 of 24Truth Table For SRAM OperationsHSB should remain HIGH for SRAM Operations.Fo

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 16 of 24Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOperatin

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 17 of 2425 CY14B102L-ZS25XCT 51-85087 44-pin TSOP II CommercialCY14B102L-ZS25XIT 51-

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 18 of 2445 CY14B102L-ZS45XCT 51-85087 44-pin TSOP II CommercialCY14B102L-ZS45XIT 51-

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 19 of 24Part Numbering NomenclatureOption:T - Tape & ReelBlank - Std.Speed:20 -

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 2 of 24Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 20 of 24Package Diagrams Figure 16. 44-Pin TSOP II (51-85087)MAXMIN.DIMENSION IN MM

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 21 of 24Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)Package Diagrams

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 22 of 24Figure 18. 54-Pin TSOP II (51-85160)Package Diagrams (continued)51-85160-*

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 23 of 24Document History Page Document Title: CY14B102L/CY14B102N 2 Mbit (256K x 8/1

Document #: 001-45754 Rev. *B Revised November 10, 2008 Page 24 of 24AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All pr

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 3 of 24Figure 3. Pin Diagram - 54 Pin TSOP II (x16)Pin DefinitionsPin Name IO Type

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 4 of 24Device OperationThe CY14B102L/CY14B102N nvSRAM is made up of twofunctional co

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 5 of 24completion of the STORE operation, theCY14B102L/CY14B102N remains disabled un

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 6 of 24Preventing AutoStoreThe AutoStore function is disabled by initiating an AutoS

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 7 of 24Maximum RatingsExceeding maximum ratings may impair the useful life of thedev

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 8 of 24AC Test ConditionsInput Pulse Levels....

PRELIMINARYCY14B102L, CY14B102NDocument #: 001-45754 Rev. *B Page 9 of 24AC Switching Characteristics ParametersDescription20 ns 25 ns 45 nsUnitCypres