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72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-05384 Rev. *F Revised March 6, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 400 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 800 MHz) at 400 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1561V18 – 8M x 8

CY7C1576V18 – 8M x 9

CY7C1563V18 – 4M x 18

CY7C1565V18 – 2M x 36

Functional Description

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and

CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II+ architecture. Similar to QDR-II archi-

tecture, QDR-II+ SRAMs consists of two separate ports: the read

port and the write port to access the memory array. The read port

has dedicated data outputs to support read operations and the

write port has dedicated data inputs to support write operations.

QDR-II+ architecture has separate data inputs and data outputs

to completely eliminate the need to “turn-around” the data bus

that exists with common IO devices. Each port is accessed

through a common address bus. Addresses for read and write

addresses are latched on alternate rising edges of the input (K)

clock. Accesses to the QDR-II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 8-bit

words (CY7C1561V18), 9-bit words (CY7C1576V18), 18-bit

words (CY7C1563V18), or 36-bit words (CY7C1565V18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K

), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current x8 1400 1300 1200 1100 mA

x9 1400 1300 1200 1100

x18 1400 1300 1200 1100

x36 1400 1300 1200 1100

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 27 28

Resumo do Conteúdo

Página 1 - CY7C1563V18, CY7C1565V18

72-Mbit QDR™-II+ SRAM 4-Word BurstArchitecture (2.5 Cycle Read Latency)CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Cypress Semiconductor Corporati

Página 2

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 10 of 28The truth table for CY7C1561V18, CY7C1576V18, CY7C1563

Página 3

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 11 of 28The write cycle description table for CY7C1576V18 foll

Página 4

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 12 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inc

Página 5

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 13 of 28IDCODEThe IDCODE instruction loads a vendor-specific,

Página 6

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 14 of 28The state diagram for the TAP controller follows. [12]

Página 7

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 15 of 28TAP Controller Block DiagramTAP Electrical Characteris

Página 8

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 16 of 28TAP AC Switching Characteristics Over the Operating Ra

Página 9

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 17 of 28Identification Register Definitions Instruction FieldV

Página 10

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 18 of 28Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit #

Página 11

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 19 of 28Power Up Sequence in QDR-II+ SRAMQDR-II+ SRAMs must be

Página 12

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 2 of 28Logic Block Diagram (CY7C1561V18)Logic Block Diagram (C

Página 13

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 20 of 28Maximum RatingsExceeding maximum ratings may impair th

Página 14

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 21 of 28IDD [22]VDD Operating Supply VDD = Max, IOUT = 0 mA,f

Página 15

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 22 of 28AC Electrical Characteristics Over the Operating Range

Página 16 - ALL INPUT PULSES

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 23 of 28Switching Characteristics Over the Operating Range [23

Página 17

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 24 of 28Switching WaveformsRead/Write/Deselect Sequence [31, 3

Página 18

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 25 of 28Ordering Information Not all of the speed, package and

Página 19 - Power Up Sequence

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 26 of 28333 CY7C1561V18-333BZC 51-85195 165-Ball Fine Pitch Ba

Página 20

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 27 of 28Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4

Página 21

Document Number: 001-05384 Rev. *F Revised March 6, 2008 Page 28 of 28QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Página 22 - Thermal Resistance

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 3 of 28Logic Block Diagram (CY7C1563V18)Logic Block Diagram (C

Página 23

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 4 of 28Pin Configuration The pin configuration for CY7C1561V18

Página 24 - Switching Waveforms

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 5 of 28CY7C1563V18 (4M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC/144

Página 25

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 6 of 28Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-

Página 26

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 7 of 28ZQ Input Output Impedance Matching Input. This input is

Página 27 - 51-85195-*A

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 8 of 28Functional OverviewThe CY7C1561V18, CY7C1576V18, CY7C15

Página 28 - Document History Page

CY7C1561V18, CY7C1576V18CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 9 of 28Depth ExpansionThe CY7C1563V18 has a port select input

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