Cypress EZ-OTG CY7C67200 Manual do Utilizador

EZ-OTG™ Programmable USBOn-The-GoCY7C67200Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #:

CY7C67200Document #: 38-08014 Rev. *G Page 10 of 78RegistersSome registers have different functions for a read vs. a writeaccess or USB host vs. USB

CY7C67200Document #: 38-08014 Rev. *G Page 11 of 78Bank Register [0xC002] [R/W]Figure 8. Bank Register Register Description The Bank register maps r

CY7C67200Document #: 38-08014 Rev. *G Page 12 of 78CPU Speed Register [0xC008] [R/W]Figure 10. CPU Speed Register Register DescriptionThe CPU Speed r

CY7C67200Document #: 38-08014 Rev. *G Page 13 of 78Power Control Register [0xC00A] [R/W]Figure 11. Power Control Register Register DescriptionThe Pow

CY7C67200Document #: 38-08014 Rev. *G Page 14 of 78Halt Enable (Bit 0)Setting this bit to ‘1’ immediately initiates HALT mode. Whilein HALT mode, onl

CY7C67200Document #: 38-08014 Rev. *G Page 15 of 78UART Interrupt Enable (Bit 3)The UART Interrupt Enable bit enables or disables thefollowing UART h

CY7C67200Document #: 38-08014 Rev. *G Page 16 of 78USB Diagnostic Register [0xC03C] [R/W]Figure 14. USB Diagnostic Register Register DescriptionThe U

CY7C67200Document #: 38-08014 Rev. *G Page 17 of 78Watchdog Timer Register [0xC00C] [R/W]Figure 15. Watchdog Timer Register Register DescriptionThe W

CY7C67200Document #: 38-08014 Rev. *G Page 18 of 78Timer n Register [R/W]• Timer 0 Register 0xC010• Timer 1 Register 0xC012Figure 16. Timer n Registe

CY7C67200Document #: 38-08014 Rev. *G Page 19 of 78Port A D+ Status (Bit 13)The Port A D+ Status bit is a read-only bit that indicates thevalue of DA

CY7C67200Document #: 38-08014 Rev. *G Page 2 of 78IntroductionEZ-OTG™ (CY7C67200) is Cypress Semiconductor’s firstUSB On-The-Go (OTG) host/peripheral

CY7C67200Document #: 38-08014 Rev. *G Page 20 of 78Host n Control Register [R/W]• Host 1 Control Register 0xC080• Host 2 Control Register 0xC0A0Figur

CY7C67200Document #: 38-08014 Rev. *G Page 21 of 78Host n Address Register [R/W]• Host 1 Address Register 0xC082• Host 2 Address Register 0xC0A2Figur

CY7C67200Document #: 38-08014 Rev. *G Page 22 of 78Host n Endpoint Status Register [R]• Host 1 Endpoint Status Register 0xC086• Host 2 Endpoint Statu

CY7C67200Document #: 38-08014 Rev. *G Page 23 of 78ACK Flag (Bit 0)The ACK Flag bit indicates two different conditions dependingon the transfer type.

CY7C67200Document #: 38-08014 Rev. *G Page 24 of 78Host n Count Result Register [R]• Host 1 Count Result Register 0xC088• Host 2 Count Result Registe

CY7C67200Document #: 38-08014 Rev. *G Page 25 of 78Host n Interrupt Enable Register [R/W]• Host 1 Interrupt Enable Register 0xC08C• Host 2 Interrupt

CY7C67200Document #: 38-08014 Rev. *G Page 26 of 78Host n Status Register [R/W]• Host 1 Status Register 0xC090• Host 2 Status Register 0xC0B0Figure 2

CY7C67200Document #: 38-08014 Rev. *G Page 27 of 78Host n SOF/EOP Count Register [R/W]• Host 1 SOF/EOP Count Register 0xC092• Host 2 SOF/EOP Count Re

CY7C67200Document #: 38-08014 Rev. *G Page 28 of 78Host n Frame Register [R]• Host 1 Frame Register 0xC096• Host 2 Frame Register 0xC0B6Figure 29. Ho

CY7C67200Document #: 38-08014 Rev. *G Page 29 of 78Figure 30. Device n Endpoint n Control Register Register DescriptionThe Device n Endpoint n Contro

CY7C67200Document #: 38-08014 Rev. *G Page 3 of 78USB InterfaceEZ-OTG has two built-in Host/Peripheral SIEs that each havea single USB transceiver, m

CY7C67200Document #: 38-08014 Rev. *G Page 30 of 78Device n Endpoint n Address Register [R/W]• Device n Endpoint 0 Address Register [Device 1: 0x0202

CY7C67200Document #: 38-08014 Rev. *G Page 31 of 78Register DescriptionThe Device n Endpoint n Count register designates the maximum packet size that

CY7C67200Document #: 38-08014 Rev. *G Page 32 of 78IN Exception Flag (Bit 8)The IN Exception Flag bit indicates when the device receivedan IN packet

CY7C67200Document #: 38-08014 Rev. *G Page 33 of 78Device n Endpoint n Count Result Register [R/W]• Device n Endpoint 0 Count Result Register [Device

CY7C67200Document #: 38-08014 Rev. *G Page 34 of 78Device n Interrupt Enable Register [R/W]• Device 1 Interrupt Enable Register 0xC08C• Device 2 Inte

CY7C67200Document #: 38-08014 Rev. *G Page 35 of 78EP5 Interrupt Enable (Bit 5)The EP5 Interrupt Enable bit enables or disables an endpointfive (EP5)

CY7C67200Document #: 38-08014 Rev. *G Page 36 of 78Device n Address Register [W]• Device 1 Address Register 0xC08E• Device 2 Address Register 0xC0AEF

CY7C67200Document #: 38-08014 Rev. *G Page 37 of 78Reset Interrupt Flag (Bit 8)The Reset Interrupt Flag bit indicates if the USB ResetDetected interr

CY7C67200Document #: 38-08014 Rev. *G Page 38 of 78Device n Frame Number Register [R]• Device 1 Frame Number Register 0xC092• Device 2 Frame Number R

CY7C67200Document #: 38-08014 Rev. *G Page 39 of 78OTG Control RegistersThere is one register dedicated for OTG operation. Thisregister is covered in

CY7C67200Document #: 38-08014 Rev. *G Page 4 of 78UART Features• Supports baud rates of 900 to 115.2K•8-N-1UART PinsI2C EEPROM InterfaceEZ-OTG provid

CY7C67200Document #: 38-08014 Rev. *G Page 40 of 78VBUS Valid Flag (Bit 0)The VBUS Valid Flag bit indicates whether OTG VBus isgreater than 4.4V. Aft

CY7C67200Document #: 38-08014 Rev. *G Page 41 of 78HSS Enable (Bit 7)The HSS Enable bit routes HSS to GPIO[15:12]. 1: HSS is routed to GPIO0: HSS is

CY7C67200Document #: 38-08014 Rev. *G Page 42 of 78Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.ReservedAll reserv

CY7C67200Document #: 38-08014 Rev. *G Page 43 of 78Register DescriptionThe GPIO 0 Direction register controls the direction of the GPIO data pins (in

CY7C67200Document #: 38-08014 Rev. *G Page 44 of 78HSS Control Register [0xC070] [R/W]Figure 48. HSS Control Register Register DescriptionThe HSS Con

CY7C67200Document #: 38-08014 Rev. *G Page 45 of 78Transmit Ready (Bit 4)The Transmit Ready bit is a read only bit that indicates if theHSS Transmit

CY7C67200Document #: 38-08014 Rev. *G Page 46 of 78HSS Transmit Gap Register [0xC074] [R/W]Figure 50. HSS Transmit Gap Register Register DescriptionT

CY7C67200Document #: 38-08014 Rev. *G Page 47 of 78HSS Receive Address Register [0xC078] [R/W]Figure 52. HSS Receive Address Register Register Descri

CY7C67200Document #: 38-08014 Rev. *G Page 48 of 78HSS Transmit Address Register [0xC07C] [R/W]Figure 54. HSS Transmit Address Register Register Desc

CY7C67200Document #: 38-08014 Rev. *G Page 49 of 78HPI Breakpoint Register [0x0140] [R] Figure 56. HPI Breakpoint Register Register DescriptionThe HP

CY7C67200Document #: 38-08014 Rev. *G Page 5 of 78Host Port Interface (HPI)EZ-OTG has an HPI interface. The HPI interface providesDMA access to the E

CY7C67200Document #: 38-08014 Rev. *G Page 50 of 78SOF/EOP2 to CPU Enable (Bit 12)The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2interrupt to the

CY7C67200Document #: 38-08014 Rev. *G Page 51 of 78SIEXmsg Register [W]• SIE1msg Register 0x0144• SIE2msg Register 0x0148 Figure 58. SIEXmsg Register

CY7C67200Document #: 38-08014 Rev. *G Page 52 of 78HPI Status Port [] [HPI: R] Figure 60. HPI Status Port Register DescriptionThe HPI Status Port pro

CY7C67200Document #: 38-08014 Rev. *G Page 53 of 78mode this read only bit indicates if any of the endpoint inter-rupts occurs on Device 2. Firmware

CY7C67200Document #: 38-08014 Rev. *G Page 54 of 783Wire Enable (Bit 15)The 3Wire Enable bit indicates if the MISO and MOSI datalines are tied togeth

CY7C67200Document #: 38-08014 Rev. *G Page 55 of 78SPI Control Register [0xC0CA] [R/W] Figure 62. SPI Control Register Register DescriptionThe SPI Co

CY7C67200Document #: 38-08014 Rev. *G Page 56 of 78Receive Bit Length (Bits [2:0])The Receive Bit Length field controls whether a full byte or partia

CY7C67200Document #: 38-08014 Rev. *G Page 57 of 78Transmit Interrupt Flag (Bit 1)The Transmit Interrupt Flag is a read only bit that indicates abyte

CY7C67200Document #: 38-08014 Rev. *G Page 58 of 78CRC Enable (Bit 13)The CRC Enable bit enables or disables the CRC operation.1: Enables CRC operati

CY7C67200Document #: 38-08014 Rev. *G Page 59 of 78Data Ready bit of the SPI Control register is set to ‘1’. Writing to this register in PIO byte mod

CY7C67200Document #: 38-08014 Rev. *G Page 6 of 78Charge Pump Features• Meets OTG Supplement Requirements, see Table 41, “DC Characteristics: Charge

CY7C67200Document #: 38-08014 Rev. *G Page 60 of 78SPI Receive Address Register [0xC0DC [R/W]Figure 71. SPI Receive Address Register Register Descrip

CY7C67200Document #: 38-08014 Rev. *G Page 61 of 78UART Control Register [0xC0E0] [R/W]Figure 73. UART Control Register Register DescriptionThe UART

CY7C67200Document #: 38-08014 Rev. *G Page 62 of 78Receive Full (Bit 1)The Receive Full bit indicates whether the receive buffer is full.It can be pr

CY7C67200Document #: 38-08014 Rev. *G Page 63 of 78Pin DiagramThe following describes the CY7C67200 48-pin FBGA.Figure 76. EZ-OTG Pin DiagramPin Desc

CY7C67200Document #: 38-08014 Rev. *G Page 64 of 78H6 GPIO20/A1 IO GPIO20: General Purpose IOA1: HPI A1F5 GPIO19/A0 IO GPIO19: General Purpose IOA0:

CY7C67200Document #: 38-08014 Rev. *G Page 65 of 78Absolute Maximum RatingsThis section lists the absolute maximum ratings. Stresses above those list

CY7C67200Document #: 38-08014 Rev. *G Page 66 of 78DC Characteristics Notes6. All tests were conducted with Charge pump off.7. ICC and ICCB values a

CY7C67200Document #: 38-08014 Rev. *G Page 67 of 78USB TransceiverUSB 2.0-compatible in full- and low-speed modes. This product was tested as complia

CY7C67200Document #: 38-08014 Rev. *G Page 68 of 78Clock Timing I2C EEPROM Timing Parameter Description Min. Typ. Max. UnitfCLKClock Frequency 12.0

CY7C67200Document #: 38-08014 Rev. *G Page 69 of 78HPI (Host Port Interface) Write Cycle Timing Note11. T = system clock period = 1/48 MHz.Parameter

CY7C67200Document #: 38-08014 Rev. *G Page 7 of 78Crystal PinsBoot Configuration InterfaceEZ-OTG can boot into any one of four modes. The mode itboot

CY7C67200Document #: 38-08014 Rev. *G Page 70 of 78HPI (Host Port Interface) Read Cycle Timing Parameter Description Min. Typ. Max. UnittASUAddress S

CY7C67200Document #: 38-08014 Rev. *G Page 71 of 78HSS BYTE Mode Transmit qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diag

CY7C67200Document #: 38-08014 Rev. *G Page 72 of 78Hardware CTS/RTS HandshaketCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min.tCTShold: H

CY7C67200Document #: 38-08014 Rev. *G Page 73 of 78Register SummaryTable 42. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11

CY7C67200Document #: 38-08014 Rev. *G Page 74 of 78R/W 0xC024 GPIO 1 Output Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000GPIO23 GPIO22 GPIO21 G

CY7C67200Document #: 38-08014 Rev. *G Page 75 of 78R/W 0xC090 Host 1 Status VBUS InterruptFlagIDInterruptFlagReserved SOF/EOPInterruptFlagReserved xx

CY7C67200Document #: 38-08014 Rev. *G Page 76 of 78R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxxData xxxx xxxxR/W 0xC0D8 SPI Transmit Address Address

CY7C67200Document #: 38-08014 Rev. *G Page 77 of 78© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change w

CY7C67200Document #: 38-08014 Rev. *G Page 78 of 78Document History PageDocument Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral

CY7C67200Document #: 38-08014 Rev. *G Page 8 of 78Minimum Hardware Requirements for Standalone Mode – Peripheral Only Power Savings and Reset Descri

CY7C67200Document #: 38-08014 Rev. *G Page 9 of 78External (Remote) Wakeup SourceThere are several possible events available to wake EZ-OTGfrom Sleep