Cypress CY7C1360C Manual do Utilizador

9-Mbit (256K x 36/512K x 18) Pipelined SRAMCY7C1360CCY7C1362CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-9

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 10 of 31READ Cycle, Begin Burst External L H L L H L X H L L-H QREAD Cycle, Begin Burst External

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 11 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1360C/CY7C1362C incorporates a serial boun

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 12 of 31TAP Controller Block DiagramPerforming a TAP ResetA RESET is performed by forcing TMS HIG

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 13 of 31IDCODEThe IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded into the i

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 14 of 313.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 15 of 31VOL2Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 VVDDQ = 2.5V 0.2 VVIHInput HIGH Volta

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 16 of 31165-ball FBGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18)Bit# ball I

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 17 of 31119-ball BGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18)Bit# ball IDS

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 18 of 31Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not te

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 19 of 31Capacitance[16]Parameter Description Test Conditions100 TQFPMax.119 BGAMax.165 FBGAMax. U

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 2 of 31.Selection Guide250 MHz 200 MHz 166 MHz UnitMaximum Access Time 2.8 3.0 3.5 nsMaximum Oper

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 20 of 31Switching Characteristics Over the Operating Range[17, 18]Parameter Description–250 –200

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 21 of 31Switching WaveformsRead Cycle Timing[23]Note: 23. On this diagram, when CE is LOW: CE1 is

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 22 of 31Write Cycle Timing[23, 24]Note: 24.Full width Write can be initiated by either GW LOW; or

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 23 of 31Read/Write Cycle Timing[23, 25, 26]Notes: 25. The data bus (Q) remains in high-Z followin

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 24 of 31ZZ Mode Timing[27, 28]Notes: 27. Device must be deselected when entering ZZ mode. See Cyc

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 25 of 31Ordering InformationNot all of the speed, package and temperature ranges are available. P

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 26 of 31200 CY7C1360C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 27 of 31250 CY7C1360C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 28 of 31Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE MO

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 29 of 31Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40 MAX.

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 3 of 31Pin Configurations AAAAA1A0NC/72MNC/36MVSSVDDNC/18MAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBV

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 30 of 31© Cypress Semiconductor Corporation, 2006. The information contained herein is subject t

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 31 of 31Document History PageDocument Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pip

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 4 of 31Pin Configurations (continued)AAAAA1A0NC/72MNC/36MVSSVDDNC/18MNCAAAAAAADQPBDQBDQBVDDQVSSQ

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 5 of 31Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQPCDQCDQDDQCDQDA

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 6 of 31Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable with JTAG)CY7C1360C (25

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 7 of 31Pin Definitions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to sele

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 8 of 31Functional OverviewAll synchronous inputs pass through input registers controlledby the ri

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 9 of 31conducted, the data presented to the DQs is written into thecorresponding address location