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36-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-05616 Rev. *F Revised January 29, 2009

Features

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600MHz) at 300 MHz for DDR-II

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1416AV18 – 4M x 8

CY7C1427AV18 – 4M x 9

CY7C1418AV18 – 2M x 18

CY7C1420AV18 – 1M x 36

Functional Description

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and

CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1416AV18

and two 9-bit words in the case of CY7C1427AV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1416AV18 and

CY7C1427AV18. On CY7C1418AV18 and CY7C1420AV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1418AV18 and two 36-bit words in the case of

CY7C1420AV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 845 795 725 600 500 mA

x9 850 800 725 600 500

x18 900 835 760 620 525

x36 990 910 825 675 570

[+] Feedback

1 2 3 4 5 6 ... 30 31

Resumo do Conteúdo

Página 1 - Burst Architecture

36-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Cypress Semiconductor Corporation • 198 Champion Court

Página 2

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 10 of 31Truth TableThe truth table for the CY7C1416AV18, CY

Página 3

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 11 of 31Write Cycle DescriptionsThe write cycle description

Página 4

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Página 5

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 13 of 31IDCODEThe IDCODE instruction loads a vendor-specifi

Página 6

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 14 of 31TAP Controller State DiagramThe state diagram for t

Página 7

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 15 of 31TAP Controller Block DiagramTAP Electrical Characte

Página 8

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 16 of 31TAP AC Switching Characteristics Over the Operating

Página 9

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 17 of 31Identification Register Definitions Instruction Fie

Página 10 - CY7C1418AV18, CY7C1420AV18

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 18 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit

Página 11

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 19 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must b

Página 12

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 2 of 31Logic Block Diagram (CY7C1416AV18)Logic Block Diagra

Página 13

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 20 of 31Maximum RatingsExceeding maximum ratings may impair

Página 14

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 21 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA,

Página 15

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 22 of 31CapacitanceTested initially and after any design or

Página 16 - [+] Feedback

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 23 of 31Switching Characteristics Over the Operating Range

Página 17

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 24 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in singl

Página 18

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 25 of 31Switching WaveformsFigure 5. Read/Write/Deselect S

Página 19 - DLL Constraints

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 26 of 31Ordering Information Not all of the speed, package

Página 20

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 27 of 31250 CY7C1416AV18-250BZC 51-85195 165-Ball Fine Pitc

Página 21

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 28 of 31167 CY7C1416AV18-167BZC 51-85195 165-Ball Fine Pitc

Página 22 - Thermal Resistance

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 29 of 31Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1

Página 23

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 3 of 31Logic Block Diagram (CY7C1418AV18)Logic Block Diagra

Página 24

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 30 of 31Document History PageDocument Title: CY7C1416AV18,

Página 25

Document Number: 38-05616 Rev. *F Revised January 29, 2009 Page 31 of 31DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress,

Página 26

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 4 of 31Pin Configuration The pin configuration for CY7C1416

Página 27

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 5 of 31CY7C1418AV18 (2M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC

Página 28

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]In

Página 29 - Package Diagram

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 7 of 31CQ Output Clock CQ Referenced with Respect to C. Thi

Página 30

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 8 of 31Functional OverviewThe CY7C1416AV18, CY7C1427AV18, C

Página 31

CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 9 of 31Depth ExpansionDepth expansion requires replicating

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