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CY7C09079V/89V/99V

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06043 Rev. *C Revised December 10, 2008

Features

■ True Dual-Ported memory cells which enable simultaneous

access of the same memory location

■ 6 Flow-Through and Pipelined devices

■ 32K x 8/9 organizations (CY7C09079V/179V)

■ 64K x 8/9 organizations (CY7C09089V/189V)

■ 128K x 8/9 organizations (CY7C09099V/199V)

■ 3 Modes

■ Flow-Through

■ Pipelined

■ Burst

■ Pipelined output mode on both ports enables fast 100 MHz

operation

■ 0.35-micron CMOS for optimum speed and power

■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)

■ 3.3V low operating power

■ Active= 115 mA (typical)

■ Standby= 10 μA (typical)

■ Fully synchronous interface for easier operation

■ Burst counters increment addresses internally

■ Shorten cycle times

■ Minimize bus noise

■ Supported in Flow-Through and Pipelined modes

■ Dual Chip Enables for easy depth expansion

■ Automatic power down

■ Commercial and Industrial temperature ranges

■ Available in 100-pin TQFP

■ Pb-free packages available

Notes

1. See page 6 for Load Conditions.

2. I/O

–I/O

for x8 devices, I/O

–I/O

for x9 devices.

3. A

–A

for 32K, A

–A

for 64K, and A

–A

for 128K devices.

Logic Block Diagram

R/W

FT/Pipe

I/O

–I/O

7/8L

Control

–A

14/15/16L

CLK

ADS

CNTEN

CNTRST

R/W

0/1

FT/Pipe

I/O

–I/O

7/8R

I/O

Control

–A

14/15/16R

CLK

ADS

CNTEN

CNTRST

0/1

I/O

Counter/

Address

Decode

True Dual-Ported

RAM Array

Counter/

Address

Decode

8/9 8/9

[2]

[3]

15/16/17

CY7C0907 9V/89V/99V

CY7C0917 9V/89V/99V

[+] Feedback

1 2 3 4 5 6 ... 20 21

Resumo do Conteúdo

Página 1 - 3.3V 32K/64K/128K x 8/9

CY7C09079V/89V/99VCY7C09179V/89V/99V3.3V 32K/64K/128K x 8/9Synchronous Dual-Port Static RAMCypress Semiconductor Corporation • 198 Champion Court • S

Página 2

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 10 of 21Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24,

Página 3

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 11 of 21Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]S

Página 4

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 12 of 21Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27,

Página 5

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 13 of 21Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 2

Página 6

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 14 of 21Figure 14. Pipelined Read with Address Counter Advance[29]Figure 15.

Página 7

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 15 of 21Figure 16. Write with Address Counter Advance (Flow-Through or Pipelin

Página 8

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 16 of 21Figure 17. Counter Reset (Pipelined Outputs)[19, 26, 32, 33]Notes32. C

Página 9

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 17 of 21Table 1. Read/Write and Enable Operation[34, 35, 36]Inputs OutputsOE C

Página 10 - CY7C09179V/89V/99V

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 18 of 21Ordering Information32K x8 3.3V Synchronous Dual-Port SRAMSpeed (ns) Or

Página 11

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 19 of 2164K x9 3.3V Synchronous Dual-Port SRAMSpeed (ns) Ordering Code Package

Página 12

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 2 of 21Functional DescriptionThe CY7C09079V/89V/99V and CY7C09179V/89V/99V areh

Página 13

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 20 of 21Package DiagramFigure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A

Página 14

Document #: 38-06043 Rev. *C Revised December 10, 2008 Page 21 of 21All products and company names mentioned in this document may be the trademarks of

Página 15

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 3 of 21Pin Configurations (continuedFigure 2. 100-Pin TQFP (Top View0 - CY7C09

Página 16

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 4 of 21Notes8. This pin is NC for CY7C09179V.9. This pin is NC for CY7C09179V a

Página 17

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 5 of 21Maximum RatingsExceeding maximum ratings may impair the useful life of t

Página 18

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 6 of 21Figure 4. AC Test Loads (Applicable to -6 and -7 only)[13]Figure 5. Lo

Página 19

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 7 of 21Notes14. Test conditions used are Load 2.15. This parameter is guarantee

Página 20

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 8 of 21Switching Waveforms (continued)Figure 6. Read Cycle for Flow-Through Ou

Página 21

CY7C09079V/89V/99VCY7C09179V/89V/99VDocument #: 38-06043 Rev. *C Page 9 of 21Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18

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