Cypress CY62167EV18 Manual do Utilizador

Consulte online ou descarregue Manual do Utilizador para Hardware Cypress CY62167EV18. Cypress CY62167EV18 User Manual Manual do Utilizador

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CY62167EV18 MoBL
®
16 Mbit (1M x 16) Static RAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05447 Rev. *G Revised March 13, 2009
Features
Very high speed: 55 ns
Wide voltage range: 1.65V to 2.25V
Ultra low standby power
Typical standby current: 1.5 μA
Maximum standby current: 12 μA
Ultra low active power
Typical active current: 2.2 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 48-ball VFBGA packages
Functional Description
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
by 99 percent when addresses are not toggling. Place the device
into standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE
and BLE are HIGH). The input and output pins (I/O
0
through I/O
15
) are placed in a high impedance state when: the
device is deselected (CE
1
HIGH or CE
2
LOW); outputs are
disabled (OE
HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE
, BLE HIGH); and a write operation is
in progress (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the Truth Table on page
9 for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Power Down
Circuit
BHE
BLE
CE
2
CE
1
1M × 16
RAM ARRAY
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
Logic Block Diagram
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Página 1 - 16 Mbit (1M x 16) Static RAM

CY62167EV18 MoBL®16 Mbit (1M x 16) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #

Página 2

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 10 of 13Ordering InformationSpeed(ns) Ordering CodePackageDiagramPackage TypeOperatingRange55CY6216

Página 3

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 11 of 13Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150Package DiagramA1A1 CORNER0.750.75Ø0.30±0.

Página 4

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 12 of 13Document History PageDocument Title: CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAMDocument

Página 5

Document #: 38-05447 Rev. *G Revised March 13, 2009 Page 13 of 13MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semico

Página 6

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 2 of 13Pin ConfigurationFigure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View [1, 2, 3]Pr

Página 7

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 3 of 13Maximum RatingsExceeding the maximum ratings may impair the useful life of thedevice. These

Página 8

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 4 of 13Thermal ResistanceTested initially and after any design or process changes that may affect t

Página 9

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 5 of 13Switching Characteristics Over the Operating Range[13, 14] Parameter Description55 nsUnitMin

Página 10 - CY62167EV18 MoBL

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 6 of 13Switching WaveformsFigure 4 shows address transition controlled read cycle waveforms.[18, 19

Página 11

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 7 of 13Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22]Figure 6. Write Cycle No. 1S

Página 12

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 8 of 13Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22]Figure 7. Write Cycl

Página 13

CY62167EV18 MoBL®Document #: 38-05447 Rev. *G Page 9 of 13Figure 9 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22]Figure 9. Write Cycle N

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