Cypress CY7C1364C Manual do Utilizador Página 1

CY7C1364C9-Mbit (256K x 32) Pipelined Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Documen

CY7C1364CDocument #: 38-05689 Rev. *E Page 10 of 18Capacitance[11]Parameter Description Test Conditions100 TQFP Max. UnitCIN Input Capacitance TA = 2

CY7C1364CDocument #: 38-05689 Rev. *E Page 11 of 18Switching Characteristics Over the Operating Range[12,13]Parameter Description–250 –200 –166 Uni

CY7C1364CDocument #: 38-05689 Rev. *E Page 12 of 18Switching Waveforms Read Cycle Timing[18]Note: 18. On this diagram, when CE is LOW, CE1 is LOW, CE

CY7C1364CDocument #: 38-05689 Rev. *E Page 13 of 18Write Cycle Timing[18,19]Note: 19.Full width Write can be initiated by either GW LOW; or by GW HIG

CY7C1364CDocument #: 38-05689 Rev. *E Page 14 of 18Read/Write Cycle Timing[18,20, 21]Notes: 20. The data bus (Q) remains in High-Z following a Write

CY7C1364CDocument #: 38-05689 Rev. *E Page 15 of 18ZZ Mode Timing[22, 23]Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descri

CY7C1364CDocument #: 38-05689 Rev. *E Page 16 of 18Ordering InformationNot all of the speed, package and temperature ranges are available. Please con

CY7C1364CDocument #: 38-05689 Rev. *E Page 17 of 18© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change

CY7C1364CDocument #: 38-05689 Rev. *E Page 18 of 18Document History PageDocument Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAMDocument Numb

CY7C1364CDocument #: 38-05689 Rev. *E Page 2 of 18Selection Guide250 MHz 200 MHz 166 MHz UnitMaximum Access Time 2.8 3.0 3.5 nsMaximum Operating Curr

CY7C1364CDocument #: 38-05689 Rev. *E Page 3 of 18Pin Configuration (continued)AAAAA1A0NCNCVSSVDDNCAAAAAAAANCDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQB

CY7C1364CDocument #: 38-05689 Rev. *E Page 4 of 18Pin Definitions Name TQFP I/O DescriptionA0, A1, A 37, 36, 32, 33, 34, 35, 43, 44, 45, 46, 47, 48,

CY7C1364CDocument #: 38-05689 Rev. *E Page 5 of 18Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

CY7C1364CDocument #: 38-05689 Rev. *E Page 6 of 18Burst SequencesThe CY7C1364C provides a two-bit wraparound counter, fedby A[1:0], that implements e

CY7C1364CDocument #: 38-05689 Rev. *E Page 7 of 18Truth Table[3, 4, 5, 6, 7, 8]Next CycleAddress Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ WriteUnselected

CY7C1364CDocument #: 38-05689 Rev. *E Page 8 of 18Truth Table for Read/Write[3, 4]Function GW BWE BWDBWCBWBBWARead HHXXXXRead HLHHHHWrite Byte A – DQ

CY7C1364CDocument #: 38-05689 Rev. *E Page 9 of 18Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Stor