Cypress CY7C1316BV18 Manual do Utilizador descarregar pdf (Página 2)

CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Document Number: 38-05621 Rev. *D Page 2 of 31

Logic Block Diagram (CY7C1316BV18)

Logic Block Diagram (CY7C1916BV18)

Write

Reg

Write

Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

NWS

[1:0]

REF

Write Add. Decode

Control

R/W

DOFF

1M x 8 Array

[7:0]

Write

Reg

Write

Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[0]

REF

Write Add. Decode

Control

R/W

DOFF

1M x 9 Array

[8:0]

[+] Feedback

1 2 3 4 5 6 7 ... 30 31

18-Mbit DDR-II SRAM 2-Word 1
Burst Architecture 1
CY7C1316BV18, CY7C1916BV18 10
CY7C1318BV18, CY7C1320BV18 10
[+] Feedback 16
Power Up Sequence 19
DLL Constraints 19
Capacitance 22
Thermal Resistance 22
Package Diagram 29

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