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PRELIMINARY

18-Mb QDR™-II SRAM 2-Word Burst Architecture

CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-05497 Rev. *A Revised June 1, 2004

Features

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 333 MHz) @ 167MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C

) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ

) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x18, and x36 configurations

• Full data coherancy , providing most current data

• Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd

• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball

(11x15 matrix)

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1310AV18 – 2M x 8

CY7C1312AV18 – 1M x 18

CY7C1314AV18 – 512K x 36

Functional Description

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are

1.8V Synchronous Pipelined SRAMs, equipped with QDR-II

architecture. QDR-II architecture consists of two separate

ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data Inputs to support Write opera-

tions. QDR-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K

clock.

Accesses to the QDR-II Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with two 8-bit words (CY7C1310AV18) or 18-bit

words (CY7C1312AV18) or 36-bit words (CY7C1314AV18)

that burst sequentially into or out of the device. Since data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K

and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

agram

(CY7C1310AV18)

CLK

(19:0)

Gen.

Control

Logic

Address

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

[7:0]

Control

Logic

Address

Reg.

BWS

[1:0]

REF

Write Add. Decode

(19:0)

1M x 8 Array

Write

Reg

Write

Reg

DOFF

[+] Feedback

1 2 3 4 5 6 ... 20 21

Resumo do Conteúdo

Página 1 - CY7C1314AV18

PRELIMINARY18-Mb QDR™-II SRAM 2-Word Burst ArchitectureCY7C1310AV18CY7C1312AV18CY7C1314AV18Cypress Semiconductor Corporation • 3901 North First Stree

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 10 of 21 Switching Characteristics Over the Operating Range[16,17]C

Página 3

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 11 of 21 Capacitance[20]Parameter Description Test Conditions Max.

Página 4

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 12 of 21Switching Waveforms[21,22,23]Notes: 21. Q00 refers to output

Página 5

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 13 of 21IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorpora

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 14 of 21is loaded into the instruction register upon power-up orwhen

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 15 of 21 Note: 24. The 0/1 next to each state represents the value a

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 16 of 21 TAP Controller Block DiagramTAP Electrical Characteristics

Página 9

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 17 of 21 TAP AC Switching Characteristics Over the Operating Range[2

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 18 of 21Identification Register DefinitionsInstruction FieldCY7C1310

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 19 of 2130 11F31 11G32 9F33 10F34 11E35 10E36 10D37 9E38 10C39 11D40

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 2 of 21 Selection Guide167 MHz 133 MHz UnitMaximum Operating Frequen

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 20 of 21 QDR SRAMs and Quad Data Rate SRAMs comprise a new family

Página 14

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 21 of 21Document History PageDocument Title: CY7C1310AV18/CY7C1312AV

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 3 of 21Pin Configurations CY7C1310AV18 (2M × 8) – 11 × 15 BGA2345671

Página 16 - TAP Controller

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 4 of 21Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-Synch

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CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 5 of 21Q[x:0]Outputs-SynchronousData Output signals. These pins driv

Página 18

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 6 of 21IntroductionFunctional OverviewThe CY7C1310AV18/CY7C1312AV18/

Página 19

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 7 of 21Depth ExpansionThe CY7C1312AV18 has a Port Select input for e

Página 20 - 51-85180-**

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 8 of 21Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18)[2, 8

Página 21

CY7C1310AV18CY7C1312AV18CY7C1314AV18 PRELIMINARYDocument #: 38-05497 Rev. *A Page 9 of 21Maximum Ratings(Above which useful life may be impaired.)Stor

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