Cypress CY7C64013C Manual do Utilizador

Full-Speed USB (12-Mbps) FunctionCY7C64013CCY7C64113CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600D

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 10 of 514.0 Product Summary Tables4.1 Pin Assignments 4.2 I/O Register SummaryI/O registers a

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 11 of 51GPIO Configuration 0x08 R/W GPIO Port Configurations 20HAPI and I2C Configuration 0x09

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 12 of 514.3 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for more details.

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 13 of 515.0 Programming Model5.1 14-Bit Program Counter (PC)The 14-bit program counter (PC) a

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 14 of 515.1.1 Program Memory Organizationafter reset Address 14-bit PC 0x0000 Program executi

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 15 of 515.2 8-Bit Accumulator (A)The accumulator is the general-purpose register for the micro

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 16 of 515.5 8-Bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP i

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 17 of 516.0 ClockingThe XTALIN and XTALOUT are the clock pins to the microcontroller. The use

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 18 of 51The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Reg

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 19 of 519.0 General-Purpose I/O (GPIO) PortsThere are up to 32 GPIO pins (P0[7:0], P1[7:0], P

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 2 of 51TABLE OF CONTENTS1.0 FEATURES ...

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 20 of 51Port 3 Data ADDRESS 0x03Special care should be taken with any unused GPIO data bits.

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 21 of 51Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The avail

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 22 of 51The amount of sink current for the DAC I/O pin is programmable over 16 values based on

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 23 of 51Bit [4..0]: Isink [x] (x= 0..4)Writing all ‘0’s to the Isink register causes 1/5 of th

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 24 of 51Timer MSB ADDRESS 0x25Bit [3:0]: Timer higher nibbleBit [7:4]: Reserved12.0 I2C and

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 25 of 51 13.0 I2C-compatible ControllerThe I2C-compatible block provides a versatile two-wir

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 26 of 51Bit 7 : MSTR ModeSetting this bit to 1 causes the I2C-compatible block to initiate a m

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 27 of 51to the data register before setting the Continue bit. To prevent false ARB Lost signal

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 28 of 5115.0 Processor Status and Control RegisterProcessor Status and Control ADDRESS 0xFFBi

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 29 of 5116.0 InterruptsInterrupts are generated by the GPIO/DAC pins, the internal timers, I2

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 3 of 51TABLE OF CONTENTS16.6 DAC Interrupt ...

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 30 of 51The interrupt controller contains a separate flip-flop for each interrupt. See Figure

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 31 of 5116.2 Interrupt LatencyInterrupt latency can be calculated from the following equation:

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 32 of 5116.7 GPIO/HAPI InterruptEach of the GPIO pins can generate an interrupt, if enabled. T

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 33 of 515. In master receive mode, after the master receives a byte of data: Firmware should r

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 34 of 51USB Status and Control ADDRESS 0x1FBits[2..0] : Control ActionSet to control action as

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 35 of 51Bits[6..0] :Device Address Firmware writes this bits during the USB enumeration proces

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 36 of 51Bit 6: Endpoint 0 IN Received 1= Token received is an IN token. 0= Token received is n

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 37 of 51Bits[5..0] : Byte CountThese counter bits indicate the number of data bytes in a trans

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 38 of 51ACK1. IN TokenHOSTDEVICESYNCINADDRCRC5ENDPSYNCDATA1/0CRC16SYNCDataToken Packet Data Pa

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 39 of 5119.0 USB Mode TablesModeThis lists the mnemonic given to the different modes that can

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 4 of 51LIST OF FIGURESFigure 6-1. Clock Oscillator On-Chip Circuit ...

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 40 of 51An “Accept” in any of the columns means that the device will respond with an ACK to a

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 41 of 51the firmware recognizes the changes that the SIE might have made during the previous t

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 42 of 511 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes1 1 1 0 Out >

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 43 of 5120.0 Register SummaryAddress Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 44 of 51Note:B: Read and WriteW: WriteR: Read21.0 Sample SchematicRESERVED0x48 Reserved Reser

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 45 of 5122.0 Absolute Maximum RatingsStorage Temperature ...

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 46 of 51DAC InterfaceRupDAC Pull-up Resistance (typical 14 kΩ) 8.0 24.0 kΩIsink0(0)DAC[7:2] Si

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 47 of 51 Figure 24-1. Clock TimingFigure 24-2. USB Data Signal TimingFigure 24-3. HAPI Read

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 48 of 5125.0 Ordering InformationOrdering Code PROM Size Package TypeOperatingRangeCY7C64013C

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 49 of 5126.0 Package Diagrams 48-Lead Shrunk Small Outline Package51-85061-*CDIMENSIONS IN IN

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 5 of 51LIST OF TABLESTable 4-1. Pin Assignments ...

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 50 of 51© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 51 of 51Document History PageDocument Title: CY7C64013C, CY7C64113C Full-Speed USB (12 Mbps) F

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 6 of 511.0 Features• Full-speed USB Microcontroller• 8-bit USB Optimized Microcontroller— Har

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 7 of 512.0 Functional OverviewThe CY7C64013C and CY7C64113C are 8-bit One Time Programmable m

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 8 of 51 Logic Block DiagramInterruptControllerPROM12-bitTimerResetWatchdogTimerPower-OnSCLKI2C

CY7C64013C CY7C64113CDocument #: 38-08001 Rev. *B Page 9 of 513.0 Pin Configurations123456791112131415161817XTALIN1081920313029333235343736393841404