Cypress CY7C1510KV18 Manual do Utilizador descarregar pdf (Página 3)

CY7C1510KV18, CY7C1525KV18

CY7C1512KV18, CY7C1514KV18

Document Number: 001-00436 Rev. *E Page 3 of 30

Logic Block Diagram (CY7C1512KV18)

Logic Block Diagram (CY7C1514KV18)

2M x 18 Array

CLK

(20:0)

Gen.

Control

Logic

Address

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(20:0)

DOFF

[17:0]

Write

Reg

2M x 18 Array

1M x 36 Array

CLK

(19:0)

Gen.

Control

Logic

Address

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(19:0)

DOFF

[35:0]

Write

Reg

1M x 36 Array

[+] Feedback

1 2 3 4 5 6 7 8 ... 29 30

72-Mbit QDR™-II SRAM 2-Word 1
Burst Architecture 1
CY7C1510KV18, CY7C1525KV18 10
CY7C1512KV18, CY7C1514KV18 10
[+] Feedback 16
Power Up Sequence 19
PLL Constraints 19
Capacitance 22
Thermal Resistance 22
Package Diagram 29
Document History Page 30

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