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8K x 8 Static RAM

1013

CY7C185

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

ust 12

1998

Features

• High speed

—15 ns

• Fast t

DOE

• Low active power

—715 mW

• Low standby power

—220 mW

• CMOS for optimum speed/power

• Easy memory expansion with CE

, CE

, and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

Functional Description

The CY7C185 is a high-performance CMOS static RAM orga-

nized as 8192 words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE

), an active HIGH

chip enable (CE

), and active LOW output enable (OE) and

three-state drivers. This device has an automatic power-down

feature (CE

or CE

), reducing the power consumption by 70%

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE

) controls the writ-

ing/reading operation of the memory. When CE

and WE in-

puts are both LOW and CE

is HIGH, data on the eight data

input/output pins (I/O

through I/O

) is written into the memory

location addressed by the address present on the address

pins (A

through A

). Reading the device is accomplished by

selecting the device and enabling the outputs, CE

and OE

active LOW, CE

active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location ad-

dressed by the information on address pins are present on the

eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE

) is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configurations

C185–1

I/O

C185–2

I/O

GND

256 x 32 x 8

ARRAY

INPUT BUFFER

COLUMN DECODER

ROW DECODER

SENSE AMPS

POWER

DOWN

I/O

Top View

DIP/SOJ/SOIC

Selection Guide

[1]

7C185–15 7C185–20 7C185–25 7C185–35

Maximum Access Time (ns) 15 20 25 35

Maximum Operating Current (mA) 130 110 100 100

Maximum Standby Current (mA) 40/15 20/15 20/15 20/15

Note:

1. For military specifications, see the CY7C185A datasheet.

1 2 3 4 5 6 7 8 9 10

Resumo do Conteúdo

Página 1 - 8K x 8 Static RAM

8K x 8 Static RAMfax id: 1013CY7C185 Cypress Semiconductor Corporation• 3901 North First Street • San Jose • CA 95134 • 408-943-2600August 12, 1998Fea

Página 2 - Electrical Characteristics

CY7C185© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporat

Página 3 - AC Test Loads and Waveforms

CY7C1852Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature ...

Página 4 - Switching Characteristics

CY7C1853Electrical Characteristics Over the Operating Range (continued)7C185–25 7C185-35Parameter Description Test Conditions Min. Max. Min. Max. Unit

Página 5 - Switching Waveforms

CY7C1854Switching Characteristics Over the Operating Range[5]7C185–15 7C185–20 7C185–25 7C185–35Parameter Description Min. Max. Min. Max. Min. Max. Mi

Página 6

CY7C1855Switching Waveforms9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.10. WE is HIGH for read cycle.11. Data I/O is High Z if OE = V

Página 7

CY7C1856Notes:14. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.15. If CE1 goes HIGH or CE2 goes

Página 8 - Ordering Information

CY7C1857Typical DC and AC Characteristics–55 25 1251.21.00.8OUTPUT SOURCE CURRENT (mA)AMBIENT TEMPERATURE (°C)0.60.40.20.0NORMALIZED I , ICCISBVCC

Página 9

CY7C1858Document #: 38–00037–KTruth TableCE1CE2WE OE Input/Output ModeH X X X High Z Deselect/Power-DownX L X X High Z Deselect/Power-DownL H H L Dat

Página 10 - Package Diagrams

CY7C1859Package Diagrams51-85014-B28-Lead (300-Mil) Molded DIP P2128-Lead (300-Mil) Molded SOIC S2151-85026-A

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