Cypress CY14B101P Especificações descarregar pdf (Página 12)

CY14B101P

Document Number: 001-44109 Rev. *O Page 12 of 36

address (0x1FFFF) is reached, the address rolls over to 0x0000

and the device continues to write.

The WEN bit is reset to ‘0’ on completion of a WRITE sequence.

Note When a burst write reaches a protected block address, it

continues the address increment into the protected space but

does not write any data to the protected memory. If the address

roll over takes the burst write to unprotected space, it resumes

writes. The same operation is true if a burst write is initiated

within a write protected block.

Figure 10. Read Instruction Timing

SCK

012345 67

765432

20212223012345 67

MSB LSB

Data

Op-Code

0000001

0000

0 0

A16

A1A2

17-bit Address

MSB LSB

D4D5D6D7

Figure 11. Burst Mode Read Instruction Timing

SCK

LSB

Op-Code

17-bit Address

MSB

LSB

01 2 3 456 7

765432

20 21 22 23

01234567 01234567

0000 00

11 0 0 00 00 0

A16

A3 A2 A1 A0

D2D3

D4D5D6D7

Data Byte 1

Data Byte N

MSB

LSB

MSB

D2D3

D4D5D6D7

D0D7

Figure 12. Write Instruction Timing

SCK

01234 5

765432

2021222301234567

MSB LSB

Data

D0D1

D5D6D7

Op-Code

00 00001

000 0

A16 A3

A1A2

17-bit Address

MSB LSB

HI-Z

Not Recommended for New Designs

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 36 37

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