Cypress CY14B101P Especificações descarregar pdf (Página 10)

CY14B101P

Document Number: 001-44109 Rev. *O Page 10 of 36

Write Protection and Block Protection

CY14B101P provides features for both software and hardware

write protection using WRDI instruction and WP

. Additionally, this

device also provides block protection mechanism through BP0

and BP1 pins of the Status Register.

The Write Enable and Disable status of the device is indicated

by WEN bit of the Status Register. The write instructions (WRSR,

WRITE, and WRTC) and nvSRAM special instruction (STORE,

RECALL, ASENB, ASDISB) need the write to be enabled (WEN

bit = 1) before they can be issued.

Write Enable (WREN) Instruction

On power-up, the device is always in the write disable state. The

following WRITE, WRSR, WRTC, or nvSRAM special instruction

must therefore be preceded by a Write Enable instruction. If the

device is not write enabled (WEN = ‘0’), it ignores the write

instructions and returns to the standby state when CS is brought

HIGH. A new CS

falling edge is required to re-initiate serial

communication. The instruction is issued following the falling

edge of CS

. When this instruction is used, the WEN bit of Status

Note After completion of a write instruction (WRSR, WRITE, or

WRTC) or nvSRAM special instruction (STORE, RECALL,

ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is

done to provide protection from any inadvertent writes.

Therefore, WREN instruction must be used before a new write

instruction is issued.

Figure 6. Read Status Register (RDSR) Instruction Timing

SCK

01234567

000001 0

MSB

LSB

HI-Z

012345 67

Data

LSB

D0D1

D5D6

MSB

Figure 7. Write Status Register (WRSR) Instruction Timing

SCK

01 23 4567

0000000

MSB

LSB

D3D7

HI-Z

012345 67

Opcode

Data in

XXX

Figure 8. WREN Instruction

0 0 0 0 0 1 1 0

SCK

HI-Z

0 1 2 3 4 5 6 7

Not Recommended for New Designs

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 36 37

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