Cypress CY14B101L Manual do Utilizador descarregar pdf (Página 9)

CY14B101LPRELIMINARY

Document #: 001-06400 Rev. *E Page 9 of 18

AC Switching Characteristics

Parameter

Description

25 ns part 35 ns part 45 ns part

Unit

Min Max Min Max Min Max

Cypress

Parameter

Alt.

Parameter

SRAM Read Cycle

ACE

ACS

Chip Enable Access Time 25 35 45 ns

[9]

Read Cycle Time 25 35 45 ns

[10]

Address Access Time 25 35 45 ns

DOE

Output Enable to Data Valid 12 15 20 ns

OHA

Output Hold After Address Change 3 3 3 ns

LZCE

[11]

Chip Enable to Output Active 3 3 3 ns

HZCE

[11]

Chip Disable to Output Inactive 10 13 15 ns

LZOE

[11]

OLZ

Output Enable to Output Active 0 0 0 ns

HZOE

[11]

OHZ

Output Disable to Output Inactive 10 13 15 ns

[7]

Chip Enable to Power Active 0 0 0 ns

[7]

Chip Disable to Power Standby 25 35 45 ns

SRAM Write Cycle

Write Cycle Time 25 35 45 ns

PWE

Write Pulse Width 20 25 30 ns

SCE

Chip Enable to End of Write 20 25 30 ns

Data SetUp to End of Write 10 12 15 ns

Data Hold After End of Write 0 0 0 ns

Address SetUp to End of Write 20 25 30 ns

Address SetUp to Start of Write 0 0 0 ns

Address Hold After End of Write 0 0 0 ns

HZWE

[11, 12]

Write Enable to Output Disable 10 13 15 ns

LZWE

[11]

Output Active after End of Write 3 3 3 ns

Notes

9. WE

must be HIGH during SRAM read cycles.

10. Device is continuously selected with CE

and OE low.

11. Measured ± 200 mV from steady state output voltage.

12. If WE

is low when CE goes low, the outputs remain in the high impedance state.

[+] Feedback [+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 18 19

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