Cypress CY14B101L Manual do Utilizador descarregar pdf (Página 11)

CY14B101LPRELIMINARY

Document #: 001-06400 Rev. *E Page 11 of 18

Switching Waveforms

SRAM Read Cycle 1(address controlled)

[9, 10, 22]

SRAM Read Cycle 2 (CE and OE controlled)

[9, 22]

t

RC

t

AA

t

OHA

ADDRESS

DQ (DATA OUT)

DATA VALID

ADDRESS

t

RC

CE

t

ACE

t

LZCE

t

PD

t

HZCE

OE

t

DOE

t

LZOE

t

HZOE

DATA VALID

ACTIVE

STANDBY

t

PU

DQ (DATA OUT)

ICC

Note

22. HSB

must remain HIGH during READ and WRITE cycles.

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