Cypress CY7C1318JV18 Manual do Utilizador descarregar pdf (Página 2)

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Document Number: 001-15271 Rev. *B Page 2 of 26

Logic Block Diagram (CY7C1316JV18)

Logic Block Diagram (CY7C1916JV18)

Write

Reg

Write

Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

[7:0]

Output

Logic

Reg.

NWS

[1:0]

REF

Write Add. Decode

Control

R/W

DOFF

1M x 8 Array

Write

Reg

Write

Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

[8:0]

Output

Logic

Reg.

BWS

[0]

REF

Write Add. Decode

Control

R/W

DOFF

1M x 9 Array

[+] Feedback [+] Feedback

1 2 3 4 5 6 7 ... 25 26

18-Mbit DDR-II SRAM 2-Word 1
Burst Architecture 1
CY7C1316JV18, CY7C1916JV18 10
CY7C1318JV18, CY7C1320JV18 10
[+] Feedback [+] Feedback 16
Power Up Waveforms 19
Capacitance 21
Thermal Resistance 21
AC Test Loads and Waveforms 21
Package Diagram 25
Document History Page 26

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