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EZ-USB NX2LP™ USB 2.0 NAND

Flash Controlle

CY7C68023/CY7C68024

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-08055 Rev. *B Revised October 5, 2005

1.0 Features

• High (480-Mbps) or full (12-Mbps) speed USB support

• Both common NAND page sizes supported

— 512bytes—Up to 1 Gbit Capacity

— 2K bytes—Up to 8 Gbit Capacity

• 8 chip enable pins

— Up to 8 NAND Flash single-device chips

— Up to 4 NAND Flash dual-device chips

• Industry standard ECC NAND Flash correction

— 1 bit per 256 correction

— 2 bit error detection

• Industry standard (SmartMedia) page management for

wear leveling algorithm, bad block handling, and

Physical to Logical management.

• Supports 8-bit NAND Flash interfaces

• Supports 30-ns, 50-ns, 100-ns NAND Flash timing

• Complies with USB Mass Storage Class Specification

rev 1.0

• CY7C68024 complies with USB 2.0 Specification for

Bus-Powered Devices (TID# 40460274)

• 43-mA Typical Active Current

• Space-saving and lead-free 56-QFN package (8 mm

8mm)

• Support for board-level manufacturing test via USB

interface

• 3.3V NAND Flash operation

• NAND Flash power management support

2.0 Introduction

The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND

Flash controller. This controller adheres to the Mass Storage

Class Bulk-Only Transport Specification. The USB port of the

NX2LP is connected to a host computer directly or via the

downstream port of a USB hub. Host software issues

commands and data to the NX2LP and receives status and

data from the NX2LP using standard USB protocol.

The NX2LP supports industry leading 8-bit NAND Flash inter-

faces and both common NAND page sizes of 512 and 2k

bytes. Eight chip enable pins allow the NX2LP to be connected

to up to eight single- or four dual-device NAND Flash chips.

Certain NX2LP features are configurable, enabling the NX2LP

to meet the needs of different designs’ requirements.

Figure 1-1. NX2LP Block Diagram

USB 2.0

Xceiver

Smart HS/

FS USB

Engine

NAND Flash

Interface

Logic

8-bit Data Bus

NAND Control Signals

EZ-USB NX2LP

Internal Control Logic

PLL

24 MHz

Xtal

VBUS

D+

D-

Data

Control

Chip Reset

LED1#

LED2#

Write Protect

Chip Enable Signals

[+] Feedback

1 2 3 4 5 6 7 8 9

Resumo do Conteúdo

Página 1 - Flash Controlle

EZ-USB NX2LP™ USB 2.0 NANDFlash ControllerCY7C68023/CY7C68024Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-9

Página 2 - 56-pin QFN

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 2 of 93.0 Pin Assignments3.1 Pin DiagramFigure 3-1. 56-pin QFN3.2 Pin Descriptions Pin Name Typ

Página 3 - CY7C68023/CY7C68024

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 3 of 916 Reserved N/A N/A Must be tied HIGH (no pull-up resistor required)17 VCC PWR PWR 3.3V su

Página 4

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 4 of 93.3 Additional Pin Descriptions3.3.1 DPLUS, DMINUSDPLUS and DMINUS are the USB signaling p

Página 5

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 5 of 94.0 ApplicationsThe NX2LP is a high-speed USB 2.0 peripheral device thatconnects NAND Fla

Página 6

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 6 of 97.0 Design Notes For The Quad Flat No Lead (QFN) PackageThe NX2LP comes in a 56-pin QFN p

Página 7

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 7 of 912.0 AC Electrical Characteristics12.1 USB TransceiverThe NX2LP’s USB interface complies

Página 8

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 8 of 9© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to

Página 9

CY7C68023/CY7C68024Document #: 38-08055 Rev. *B Page 9 of 9Document History PageDescription Title: CY7C68023/CY7C68024 EZ-USB NX2LP™ USB 2.0 NAND Fla

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