Cypress AutoStore STK17T88 Manual do Utilizador

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STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-52040 Rev. *A Revised March 17, 2009
Features
nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
Capacitor or Battery Backup for RTC
25, 45 ns Read Access and R/W Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year Nonvolatile Data Retention
Single 3V +20%, -10% Power Supply
Commercial and Industrial Temperatures
48-pin 300-mil SSOP Package (RoHS-Compliant)
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
ROW DECODER INPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A
13
– A
0
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
V
CC
V
CAP
RTC
MUX
A
14
– A
0
X
1
X
2
INT
V
RTCbat
V
RTCcap
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
A
0
A
1
A
2
A
3
A
4
A
10
Quantum Trap
512 X 512
STATIC RAM
ARRAY
512 X 512
Logic Block Diagram
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Resumo do Conteúdo

Página 1 - Real Time Clock

STK17T8832K x 8 AutoStore™ nvSRAM withReal Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600Doc

Página 2

STK17T88Document Number: 001-52040 Rev. *A Page 10 of 22Hardware STORE CycleFigure 11. Hardware STORE CycleSoft Sequence CommandsFigure 12. Soft Se

Página 3

STK17T88Document Number: 001-52040 Rev. *A Page 11 of 22MODE SelectionE W G A14-A0Mode I/O Power NotesH X X X Not Selected Output High Z StandbyL H L

Página 4

STK17T88Document Number: 001-52040 Rev. *A Page 12 of 22nvSRAM OperationThe STK17T88 nvSRAM is made up of two functional compo-nents paired in the sa

Página 5

STK17T88Document Number: 001-52040 Rev. *A Page 13 of 22Software STOREData can be transferred from the SRAM to the nonvolatilememory by a software ad

Página 6

STK17T88Document Number: 001-52040 Rev. *A Page 14 of 22Real Time ClockThe clock registers maintain time up to 9,999 years inone-second increments. T

Página 7

STK17T88Document Number: 001-52040 Rev. *A Page 15 of 22minute, have one second either shortened by 128 or lengthenedby 256 oscillator cycles.If a bi

Página 8

STK17T88Document Number: 001-52040 Rev. *A Page 16 of 22Figure 15 is a functional diagram of the interrupt logic.Figure 15. Interrupt Block DiagramI

Página 9

STK17T88Document Number: 001-52040 Rev. *A Page 17 of 22RTC Register Map*A binary value, not a BCD value.0 - Not implemented, reserved for future use

Página 10 - STK17T88

STK17T88Document Number: 001-52040 Rev. *A Page 18 of 22Register Map Detail0x7FFFReal Time Clock – Years D7 D6 D5 D4 D3 D2 D1 D010s Years YearsContai

Página 11

STK17T88Document Number: 001-52040 Rev. *A Page 19 of 22WDW Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out valu

Página 12

STK17T88Document Number: 001-52040 Rev. *A Page 2 of 22Pin ConfigurationsFigure 1. 48-Pin SSOPVSSA14A12A7A6DQ0DQ1VCCDQ2A3A2A1VCAPA13A6A9A11A10DQ7DQ6

Página 13

STK17T88Document Number: 001-52040 Rev. *A Page 20 of 22Ordering Codes0x7FF0FlagsD7 D6 D5 D4 D3 D2 D1 D0WDF AF PF OSCF 0 CAL W RWDF Watchdog Timer Fl

Página 14

STK17T88Document Number: 001-52040 Rev. *A Page 21 of 22Package DiagramFigure 16. 48-Pin SSOP (51-85061)51-85061-*C[+] Feedback

Página 15

Document Number: 001-52040 Rev. *A Revised March 17, 2009 Page 22 of 22AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor C

Página 16

STK17T88Document Number: 001-52040 Rev. *A Page 3 of 22Absolute Maximum RatingsVoltage on Input Relative to Ground...–0.5V to 4.1VVolta

Página 17

STK17T88Document Number: 001-52040 Rev. *A Page 4 of 22AC Test ConditionsInput Pulse Levels...0V to

Página 18

STK17T88Document Number: 001-52040 Rev. *A Page 5 of 22RTC DC CharacteristicsFigure 4. RTC Component ConfigurationSymbol ParameterCommercial Industr

Página 19

STK17T88Document Number: 001-52040 Rev. *A Page 6 of 22SRAM READ Cycles #1 and #2Figure 5. SRAM READ Cycle #1: Address Controlled[3,4,6]Figure 6. S

Página 20

STK17T88Document Number: 001-52040 Rev. *A Page 7 of 22SRAM WRITE Cycles #1 and #2Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8]Figure 8. SRAM W

Página 21 - 51-85061-*C

STK17T88Document Number: 001-52040 Rev. *A Page 8 of 22AutoStore/Power Up RECALLFigure 9. AutoStore Power Up RECALLNotes9. tHRECALL starts from the

Página 22

STK17T88Document Number: 001-52040 Rev. *A Page 9 of 22Figure 10. Software Store/Recall Cycle: E CONTROLLED[13]Software-Controlled STORE/RECALL Cycl

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