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30 Document No. 001-64846 Rev. *I Getting Started with CapSense

Rearranging the equation gives the following result:

   



  



  Equation 13

The previous equation has various integral solutions. For simplicity, this example uses N1 = 4 and N2 = 10.

Substituting these values in the previous equation generates the values:

    



  



  Equation 14

Thus, Period Value is 249. To have a 50-percent duty cycle, the Compare value for the PWM is set as:



  



 



  



  



Equation 15

User module parameters are matched as shown in the following table.

Table 2-1. PWM8 User Module Parameters

Parameter

Value

Name

PWM

Configuration

8 bit

Clock

VC2

Period

249

Pulse Width

125

Compare Type

Less than

Interrupt Type

Compare True

Clock Sync

Sync to SysClk

Note that the CSD user module automatically varies the clock dividers based on scan speed and resolution settings

of the CSD user module. Therefore, re-enter the clock dividers every time the PWM module is invoked by writing the

values directly to the configuration register OSC_CR1. For details about the Configuration register OSC_CR1, see

the Technical Reference Manual.

The clock dividers VC1, VC2, and VC3 vary with the CSD scan speed and resolution, as shown in Table 2-2 and

Table 2-3.

Table 2-2. Scan Speed versus VC1 Divider

Scanning Speed

VC1

Ultra fast

Fast

Normal

Slow

Table 2-3. Resolution versus VC2 and VC3 Clock Dividers

Resolution

Bits

VC2

VC3

128

256

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 74 75

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