Cypress Perform CY7C68013 Manual do Utilizador Página 1

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016AEZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral ControllerCypress Semiconductor Corporation •

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 10 of 623.12 Endpoint RAM3.12.1 Size 3× 64 bytes (Endpoints 0 and 1)

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 11 of 623.12.5 Default Full-Speed Alternate Settings 3.12.6 Default Hi

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 12 of 623.13.3 GPIF and FIFO Clock RatesAn 8051 register bit selects on

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 13 of 623.18 I2C ControllerFX2LP has one I2C port that is driven by two

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 14 of 623.20 CY7C68013A/14A and CY7C68015A/16A DifferencesCY7C68013A is

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 15 of 62Figure 6. SignalRDY0RDY1CTL0CTL1CTL2INT0#/PA0INT1#/PA1PA2WU2/PA

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 16 of 62Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin AssignmentCLKO

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 17 of 62Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin AssignmentPD0/

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 18 of 62Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment12345

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 19 of 62Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment2827

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 2 of 62 1.1 Features (CY7C68013A/14A only) CY7C68014A: Ideal for batte

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 20 of 62Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View123

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 21 of 624.1 CY7C68013A/15A Pin DescriptionsThe FX2LP Pin Descriptions f

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 22 of 6234 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 23 of 6285 70 43 36 7F PA3 or WU2IO/Z I(PA3)Multiplexed pin whose functi

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 24 of 6255 45 30 23 5G PB5 orFD[5]IO/Z I(PB5)Multiplexed pin whose funct

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 25 of 62104 82 54 47 6B PD2 orFD[10]IO/Z I(PD2)Multiplexed pin whose fun

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 26 of 62112 90 PE4 orRXD1OUTIO/Z I(PE4)Multiplexed pin whose function is

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 27 of 6270 55 37 30 7G CTL1 orFLAGBO/Z H Multiplexed pin whose function

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 28 of 6250 40 TXD0 Output H TXD0 is the active-HIGH TXD0 output from 805

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 29 of 625. Register SummaryFX2LP register bit definitions are described

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 3 of 622. Applications Portable video recorder MPEG/TV conversion DS

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 30 of 62E62B 1 ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 31 of 62E65D 1 USBIRQ[12]USB Interrupt Requests 0 EP0ACK HSGRANT URES SU

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 32 of 62E69D 1 EP8BCL[11] Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 B

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 33 of 62E6CB 1 FLOWSTB Flowstate Strobe ConfigurationSLAVE RDYASYNC CTLT

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 34 of 62xxxx I²C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx[1

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 35 of 62BE 1 GPIFSGLDATLX[13]GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 36 of 626. Absolute Maximum RatingsStorage Temperature...

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 37 of 629. DC Characteristics 9.1 USB TransceiverUSB 2.0 compliant in

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 38 of 6210.2 Program Memory Read Figure 12. Program Memory Read Timing

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 39 of 6210.3 Data Memory Read Figure 13. Data Memory Read Timing Diagr

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 4 of 623.5 USB Boot MethodsDuring the power up sequence, internal logic

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 40 of 6210.4 Data Memory WriteFigure 14. Data Memory Write Timing Diag

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 41 of 6210.5 PORTC Strobe Feature TimingsThe RD# and WR# are present in

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 42 of 6210.6 GPIF Synchronous SignalsFigure 17. GPIF Synchronous Signa

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 43 of 6210.7 Slave FIFO Synchronous ReadFigure 18. Slave FIFO Synchron

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 44 of 6210.8 Slave FIFO Asynchronous ReadFigure 19. Slave FIFO Asynchr

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 45 of 6210.9 Slave FIFO Synchronous WriteFigure 20. Slave FIFO Synchro

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 46 of 6210.10 Slave FIFO Asynchronous WriteFigure 21. Slave FIFO Async

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 47 of 62There is no specific timing requirement that should be met foras

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 48 of 6210.13 Slave FIFO Output EnableFigure 25. Slave FIFO Output En

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 49 of 6210.15 Slave FIFO Synchronous AddressFigure 27. Slave FIFO Syn

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 5 of 62The FX2LP jump instruction is encoded as follows:If Autovectoring

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 50 of 6210.17 Sequence Diagram10.17.1 Single and Burst Synchronous Rea

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 51 of 6210.17.2 Single and Burst Synchronous WriteFigure 31. Slave FI

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 52 of 6210.17.3 Sequence Diagram of a Single and Burst Asynchronous Rea

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 53 of 6210.17.4 Sequence Diagram of a Single and Burst Asynchronous Wri

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 54 of 6211. Ordering InformationTable 33. Ordering InformationOrdering

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 55 of 6212. Package DiagramsThe FX2LP is available in five packages: 5

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 56 of 62Package Diagrams (continued)51-85144-*DFigure 36. 56-Lead QFN 8

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 57 of 62 Package Diagrams (continued)NOTE:1. JEDEC STD REF MS-0262. BODY

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 58 of 62Package Diagrams (continued)NOTE:1. JEDEC STD REF MS-0262. BODY

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 59 of 6213. PCB Layout RecommendationsFollow these recommendations to e

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 6 of 62If Autovectoring is enabled (AV4EN = 1 in the INTSET-UPregister),

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 60 of 6214. Quad Flat Package No Leads (QFN) Package Design NotesElectr

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 61 of 62Document History Page Document Title: CY7C68013A, CY7C68014A, C

Document #: 38-08032 Rev. *L Revised February 8, 2008 Page 62 of 62Purchase of I2C components from Cypress, or one of its sublicensed Associated Compa

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 7 of 62 3.9.2 Wakeup PinsThe 8051 puts itself and the rest of the chip

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 8 of 62Figure 3. Internal Code Memory, EA = 0Inside FX2LP Outside FX2LP

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *L Page 9 of 62Figure 4. External Code Memory, EA = 13.11 Register AddressesIn