Cypress AutoStore STK17TA8 Manual do Utilizador descarregar pdf (Página 6)

STK17TA8

Document #: 001-52039 Rev. ** Page 6 of 23

SRAM READ Cycles #1 and #2

Figure 5. SRAM READ Cycle #1: Address Controlled

[3, 4, 6]

Figure 6. SRAM READ Cycle #2: E and G Controlled

[3, 6]

Notes

3. W

must be high during SRAM READ cycles.

4. Device is continuously selected with E

and G both low

5. Measured ± 200mV from steady state output voltage.

6. HSB

must remain high during READ and WRITE cycles.

NO.

Symbols

Parameter

STK17TA8-25 STK17TA8-45

Units

#1 #2 Alt. Min Max Min Max

ELQV

ACS

Chip Enable Access Time 25 45 ns

AVAV

[3]

ELEH

[3]

Read Cycle Time 25 45 ns

AVQV

[4]

AVQV

[4]

Address Access Time 25 45 ns

GLQV

Output Enable to Data Valid 12 20 ns

AXQX

[4]

AXQX

[4]

Output Hold after Address Change 3 3 ns

ELQX

Address Change or Chip Enable to Output Active 3 3 ns

EHQZ

[5]

Address Change or Chip Disable to Output

Inactive

10 15 ns

GLQX

OLZ

Output Enable to Output Active 0 0 ns

GHQZ

[5]

OHZ

Output Disable to Output Inactive 10 15 ns

10 t

ELICCL

[2]

Chip Enable to Power Active 0 0 ns

11 t

EHICCH

[2]

Chip Disable to Power Standby 25 45 ns

DATA VALID

AXQX

AVQV

DQ (DATA OUT)

ADDRESS

AVAV

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 ... 22 23

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