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18-Mbit DDR-II SRAM 4-Word

Burst Architecture

CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-07161 Rev. *D Revised June 18, 2008

Features

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1317CV18 – 2M x 8

CY7C1917CV18 – 2M x 9

CY7C1319CV18 – 1M x 18

CY7C1321CV18 – 512K x 36

Functional Description

The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and

CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a two-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with four 8-bit words in the case of CY7C1317CV18

and four 9-bit words in the case of CY7C1917CV18 that burst

sequentially into or out of the device. The burst counter always

starts with a ‘00’ internally in the case of CY7C1317CV18 and

CY7C1917CV18. For CY7C1319CV18 and CY7C1321CV18,

the burst counter takes in the least two significant bits of the

external address and bursts four 18-bit words in the case of

CY7C1319CV18, and four 36-bit words in the case of

CY7C1321CV18, sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 770 720 670 580 515 mA

x9 770 720 670 580 515

x18 810 760 700 600 540

x36 890 830 765 655 600

[+] Feedback

1 2 3 4 5 6 ... 30 31

Resumo do Conteúdo

Página 1 - Burst Architecture

18-Mbit DDR-II SRAM 4-WordBurst ArchitectureCY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Cypress Semiconductor Corporation • 198 Champion Court

Página 2

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 10 of 31Application ExampleFigure 1 shows two DDR-II used

Página 3

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 11 of 31Burst Address Table (CY7C1319CV18, CY7C1321CV18)Fi

Página 4

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 12 of 31Write Cycle DescriptionsThe write cycle descriptio

Página 5

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 13 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Página 6

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 14 of 31IDCODEThe IDCODE instruction loads a vendor-specif

Página 7

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 15 of 31TAP Controller State DiagramThe state diagram for

Página 8

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 16 of 31TAP Controller Block DiagramTAP Electrical Charact

Página 9

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 17 of 31TAP AC Switching Characteristics Over the Operatin

Página 10 - CY7C1319CV18, CY7C1321CV18

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 18 of 31Identification Register Definitions Instruction Fi

Página 11

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 19 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Página 12

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 2 of 31Logic Block Diagram (CY7C1317CV18)Logic Block Diagr

Página 13

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 20 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must

Página 14

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 21 of 31Maximum RatingsExceeding maximum ratings may impai

Página 15

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 22 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA

Página 16

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 23 of 31CapacitanceTested initially and after any design o

Página 17 - [+] Feedback

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 24 of 31Switching CharacteristicsOver the Operating Range

Página 18

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 25 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in sing

Página 19

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 26 of 31Switching WaveformsFigure 5. Read/Write/Deselect

Página 20 - DLL Constraints

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 27 of 31Ordering Information Not all of the speed, package

Página 21

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 28 of 31250 CY7C1317CV18-250BZC 51-85180 165-Ball Fine Pit

Página 22

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 29 of 31167 CY7C1317CV18-167BZC 51-85180 165-Ball Fine Pit

Página 23 - Thermal Resistance

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 3 of 31Logic Block Diagram (CY7C1319CV18)Logic Block Diagr

Página 24

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 30 of 31Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x

Página 25

Document Number: 001-07161 Rev. *D Revised June 18, 2008 Page 31 of 31QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Página 26

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 4 of 31Pin Configuration The pin configuration for CY7C131

Página 27

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 5 of 31CY7C1319CV18 (1M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ N

Página 28

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]I

Página 29

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 7 of 31CQ Output Clock CQ Referenced with Respect to C. Th

Página 30 - Package Diagram

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 8 of 31Functional OverviewThe CY7C1317CV18, CY7C1917CV18,

Página 31

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 9 of 31after the read(s), the stored data from the earlier

Modelos relacionados CY7C1321CV18 | CY7C1317CV18 |

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Modelos relacionados CY7C1321CV18 | CY7C1317CV18 |

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